abstract

This paper investigates the design challenges and trade-offs involved in implementing sub-threshold Very Large Scale Integration (VLSI) circuits for Internet of Things (IoT) applications. The study examines critical issues such as increased delay, leakage power, and performance variability, alongside techniques like Adaptive Voltage Scaling (AVS), body biasing, and leakage reduction. Data is collected through simulation of sub-threshold circuits under varying conditions, followed by validation using fabricated prototypes. Descriptive and trade-off analyses reveal that while individual techniques such as AVS and MTCMOS offer distinct advantages, their integration provides a comprehensive solution to the challenges of sub-threshold operation. The study highlights the need for holistic design strategies that balance energy efficiency, reliability, and cost, enabling scalable applications in IoT devices.